1. Field of the Invention
This invention relates to electronic circuitry and, more particularly, to a serializer that contains multiple multiplexing cells arranged in stages, where each cell contains fewer circuit elements and consumes less power than conventional multiplexing cells.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Communication between nodes of a communication system typically involves a serial bitstream. The bitstream can be formatted in numerous ways and is sent across a wire or wireless medium between nodes of the network. Examples of serial bitstream transfer protocols include Ethernet and Synchronous Optical Network (“SONET”), as well as numerous others.
An integral part of the serialized communication between nodes is the transceiver associated with each node. A transceiver, having both a receiver and a transmitter, functions to convert the serial bitstream to a parallel datastream, if necessary. The conversion from a relatively high bit rate serial bitstream to a relatively low rate parallel datastream takes place within a receiver, and is often referred to as deserialization. Conversely, the conversion from a parallel datastream to a serial bitstream occurs within a transmitter, and is often referred to as serialization.
The serializer and deserializer of the transceiver are normally found within the physical media attachment (“PMA”) sublayer of the transceiver. The serializer/deserializer is responsible for forwarding the datastreams between the upper layers of, for example, the Open System Interconnection (“OSI”) model and the PMA sublayer. As the bit transfer rate of the serial bitstream increases, power consumption within the serializer/deserializer can also substantially increase. This is due, in part, to the time-division multiplexing and demultiplexing operations that take place at or near the bit transfer rate.
In its most basic form, a shift register can be used to construct a serializer/deserializer operating at slower bit rates. After the shift register in a serializer receives a parallel dataword, a clock signal shifts the parallel bits through each stage of the register to output the corresponding serial bitstream from a register element in the last stage. As the bit rate increases, however, clocking the data storage elements of the shift registers at full, or even half rates, may cause the serializer to consume undesirable amounts of power.
A particular form of serializer, which can operate at very high clock rates, is often referred to as a “pipelined serializer” (sometimes also called a “systolic serializer”). A pipelined serializer essentially arranges a plurality of multiplexing cells (or “cells”) into stages. Subsequent stages are clocked at successively faster clock rates than previous stages. This allows for a majority of the multiplexing cells, especially in the front-end stages, to operate at much slower clock rates than the rate at which the serial bitstream is transmitted (i.e., the “serial data rate”). Since the “power-delay product” usually scales with frequency, circuits become increasingly less power efficient at higher frequencies. It then follows that power can be reduced in a pipelined serializer by reducing the number of multiplexing cells operating at the higher frequencies.
Pipelined serializers demonstrate substantial power savings over conventional shift registers, which are usually clocked at the serial data rate. However, pipelined serializers typically use multiple latches within each multiplexing cell. Regardless of clock rate, a multiplexing cell having more data storage elements (e.g., latches) consumes more power than a cell having fewer latches. In addition, multiplexing cells within conventional pipelined serializers typically include a relatively large number of latches and, therefore, are constrained to having a minimum power consumption level. Such a minimum power consumption level is often intolerable in many applications. In portable applications, for example, conventional multiplexing cells found within rather large n-to-1 serializers (where “n” is the input word length) may consume undesirable amounts of power as bit rates approach the technological limits. Finally, due to the excessive number of latches within each multiplexing cell, conventional pipelined serializers must often contend with extensive clock routing, undesirably long latency values and large area penalties.
Therefore, it would be desirable to introduce a multiplexing cell within a pipelined serializer that consumes less power than conventional multiplexing cells. It would also be desirable to decrease the overall number of data elements in the pipelined serializer, so as to reduce the fanout requirements of the clock signals supplied to the components of the serializer. A smaller and less power consumptive multiplexing cell can be used in large n-to-1 serializers, (where n might exceed 16, 32, or even 64) and/or within serializers operating at substantially high data rates.